000			06489cam a2200865 i 4500
001			ocn884962060
003			OCoLC
005			20230823095425.0
006			m o d
007			cr |||||||||||
008			140729s2014 enk ob 001 0 eng
010			_a 2014030064
040			_aDLC _beng _erda _epn _cDLC _dN$T _dIDEBK _dDG1 _dYDXCP _dOCLCF _dCDX _dCOO _dUNBCA _dEBLCP _dRECBK _dDEBSZ _dOCLCQ _dVT2 _dDEBBG
019			_a896800073 _a900726008 _a908280453
020			_a9781118958278 _q(ePub)
020			_a1118958276 _q(ePub)
020			_a9781118958261 _q(Adobe PDF)
020			_a1118958268 _q(Adobe PDF)
020			_a9781118958254
020			_a111895825X
020			_a1118447743 _q(cloth)
020			_a9781118447741 _q(cloth)
020			_a9781322317595 _q(MyiLibrary)
020			_a1322317593 _q(MyiLibrary)
020			_z9781118447741 _q(cloth)
028	0	1	_aEB00590480 _bRecorded Books
029	1		_aAU@ _b000053637244
029	1		_aCHBIS _b010442237
029	1		_aCHVBK _b334087147
029	1		_aDEBSZ _b431832765
029	1		_aNZ1 _b15913239
029	1		_aGBVCP _b815088248
029	1		_aDEBSZ _b456575456
029	1		_aDEBBG _bBV043397001
035			_a(OCoLC)884962060 _z(OCoLC)896800073 _z(OCoLC)900726008 _z(OCoLC)908280453
042			_apcc
050	0	0	_aTK7874.84
072		7	_aTEC _x009070 _2bisacsh
082	0	0	_a621.381 _223
049			_aMAIN
245	0	0	_aEmerging nanoelectronic devices / _cedited by Dr An Chen, Dr James Hutchby, Dr Victor Zhirnov, Dr George Bourianoff.
264		1	_aChichester, West Sussex, United Kingdom : _bWiley, _c2014.
300			_a1 online resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bn _2rdamedia
338			_aonline resource _bnc _2rdacarrier
504			_aIncludes bibliographical references and index.
588	0		_aPrint version record and CIP data provided by publisher.
505	0		_aEmerging Nanoelectronic Devices; Contents; Preface; List of Contributors; Acronyms; Part One: Introduction; 1. The Nanoelectronics Roadmap; 1.1 Introduction; 1.2 Technology Scaling: Impact and Issues; 1.3 Technology Scaling: Scaling Limits of Charge-based Devices; 1.4 The International Technology Roadmap for Semiconductors; 1.5 ITRS Emerging Research Devices International Technology Working Group; 1.5.1 ERD Editorial Team; 1.5.2 Vision and Mission; 1.5.3 Scope; 1.6 Guiding Performance Criteria; 1.6.1 Nanoinformation Processing; 1.6.2 Nanoelectronic Device Taxonomy.
505	8		_a1.6.3 Fundamental Guiding Principles -- ``Beyond CMOS ́ ́ Information Processing1.6.4 Current Technology Requirements for CMOS Extension and Beyond CMOS Memory and Logic Technologies; 1.7 Selection of Nanodevices as Technology Entries; 1.8 Perspectives; References; 2. What Constitutes a Nanoswitch? A Perspective; 2.1 The Search for a Better Switch; 2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain; 2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain?; 2.3.1 Operation of an MTJ; 2.3.2 W-R Unit with Electrical Isolation; 2.3.3 Does This W-R Unit Have Gain?
505	8		_a2.4 Giant Spin Hall Effect: A Route to Gain2.4.1 Concatenability; 2.4.2 Proof of Gain and Directionality; 2.5 Other Possibilities for Switches with Gain; 2.5.1 All-spin Logic; 2.6 What do Alternative Switches Have to Offer?; 2.6.1 Energy-Delay Product; 2.6.2 Beyond Boolean Logic; 2.7 Perspective; 2.8 Summary; Acknowledgments; References; Part Two: Nanoelectronic Memories; 3. Memory Technologies: Status and Perspectives; 3.1 Introduction: Baseline Memory Technologies; 3.2 Essential Physics of Charge-based Memory; 3.3 Dynamic Random Access Memory.
505	8		_a3.3.1 Total Energy Required to Create/Maintain the Content of a Memory Cell3.3.2 DRAM Access Time (WRITE or READ); 3.3.3 Energy-Space-Time Compromise for DRAM; 3.4 Flash Memory; 3.4.1 Store; 3.4.2 Write; 3.4.3 Read; 3.4.4 Energetics of Flash Memory; 3.5 Static Random Access Memory; 3.5.1 SRAM Access Time; 3.5.2 SRAM Scaling; 3.6 Summary and Perspective; Appendix: Memory Array Interconnects; Acknowledgments; References; 4. Spin Transfer Torque Random Access Memory; 4.1 Chapter Overview; 4.2 Spin Transfer Torque; 4.2.1 Background of Spin Transfer Torque.
505	8		_a4.2.2 Experimental Observation of Spin Transfer Torque4.3 STT-RAM Operation; 4.3.1 Design of STT-RAM Cells; 4.3.2 Key Parameters for Operation; 4.4 STT-RAM with Perpendicular Anisotropy; 4.5 Stack and Material Engineering for Jc Reduction; 4.5.1 Dual Pinned Structure; 4.5.2 Nanocurrent Channel Structure Design; 4.5.3 Electric Field Assisted Switching; 4.6 Ultra-Fast Switching of MTJs; 4.7 Spin-Orbit Torques for Memory Application; 4.8 Current Demonstrations for STT-RAM; 4.9 Summary and Perspectives; References; 5. Phase Change Memory; 5.1 Introduction; 5.2 Device Operation.
520			_aEmerging Nanoelectronic Devices focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future. This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh.
650		0	_aNanoelectronics.
650		0	_aNanoelectromechanical systems.
650		0	_aNanostructured materials.
650		4	_aNanoelectromechanical systems.
650		4	_aNanoelectronics.
650		4	_aNanostructured materials.
650		7	_aTECHNOLOGY & ENGINEERING _xMechanical. _2bisacsh
650		7	_aNanoelectromechanical systems. _2fast _0(OCoLC)fst01741807
650		7	_aNanoelectronics. _2fast _0(OCoLC)fst01741867
650		7	_aNanostructured materials. _2fast _0(OCoLC)fst01032630
655		4	_aElectronic books.
655		0	_aElectronic books.
700	1		_aChen, An _c(Electronics engineer), _eeditor.
700	1		_aHutchby, James, _eeditor.
700	1		_aZhirnov, Victor V., _eeditor.
700	1		_aBourianoff, George, _eeditor.
776	0	8	_iPrint version: _tEmerging nanoelectronic devices. _dChichester, West Sussex, United Kingdom : John Wiley & Sons, 2014 _z9781118447741 _w(DLC) 2014029299
856	4	0	_uhttp://dx.doi.org/10.1002/9781118958254 _zWiley Online Library
994			_a92 _bDG1
999			_c21584 _d21543
526			_bps